1. Field
Example embodiments are related to a semiconductor memory device and methods of forming the same, more particularly, related to a non-volatile semiconductor device and methods of forming the same.
2. Description of Related Art
Generally, a semiconductor memory device may be sorted in to a volatile memory device, where stored data dissipates when power supply is stopped, and a non-volatile memory device, which may be capable of retaining stored data when power supply is stopped. There may be a floating gate-type and a charge trap-type in a non-volatile memory device, according to a type of data storage layer which constitutes a unit cell. The floating gate-type memory device may be limited in higher integration, and may require higher power consumption. Therefore, a charge trap-type memory device is being researched.
In the related art, an example of a PROM (Programmable Read Only Memory) having charge trapping layer may be disclosed. Using a data programming and reading method, 2-bit data per memory cell may be retained. FIG. 1 illustrates a memory cell of a SONOS semiconductor memory device capable of retaining 2-bit data per memory cell of the related art.
Referring to FIG. 1, a tunnel insulation layer 20, a charge trapping layer 30, a blocking insulation layer 40, and a gate electrode 50 may be stacked sequentially on a semiconductor substrate 10. Source/drain regions 12 and 14 may be disposed on the semiconductor substrate 10 proximate to the gate electrode 50. The semiconductor memory device may store charge in charge trapping sites A and B on both ends of the charge trapping layer 30.
A migration of the charge trapped at the charge trapping layer 30 may occur. If migration of charge occurs, fluctuation in the threshold voltage may arise causing deterioration of the device reliability. In addition, interference may arise by the charge stored in the charge trapping sites A and B.
As the design rule is decreased, a short channel effect may occur, and also, a problem of shortening the distance between the charge trapping sites A and B may occur causing a decrease in the reliability of the device.